1. Technical Field
This invention generally relates to integrated circuit capacitors, and more specifically relates to deep trench capacitors.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) markets. One particular area of concern in DRAM design is the storage capacitor used to store each memory cell. The density of DRAM designs is to a great extent limited to by the feature size of the storage capacitor. Capacitors by definition store charge between electrodes. In most integrated capacitors used in DRAM applications a "storage node" or "storage electrode" is connected to DRAM circuitry, while a "counter electrode" or "plate" is generally connected to a fixed potential.
The charge stored in the storage capacitor is subject to current leakage and for that reason the DRAM must be refreshed periodically. The time allowed between refresh without excess charge leakage is the data retention time, which is determined by the amount of charge stored at the beginning of the storage cycle and the amount of leakage current through different kinds of leakage mechanisms. For various reasons it is often preferable to minimize the leakage mechanisms so as to extend the time allowed between refresh cycles.
Several methods have been used to facilitate the shrinkage of the capacitor feature size while maintaining sufficient capacitance. For example, stacked capacitors have been located above the transfer devices. Unfortunately, this approach presents difficulties with topography and with connecting the capacitors.
Another approach has been the use of trench capacitors as storage capacitors. Trench capacitors extend the storage node into the substrate to increase the capacitance without increasing the area used on the device. The trench capacitor design typically uses a highly conductive single crystal silicon substrate as the counter electrode, and a highly conductive polycrystalline silicon in a deep trench as the storage electrode of the capacitor. By extending the capacitor in the vertical dimension trench capacitors allow the capacitor feature size to be decreased without decreasing the resulting capacitance.
The trench capacitor was further refined by the use of a substrate plate trench design. Referring to FIG. 1, there is shown a schematic cross-sectional view of the basic Substrate Plate Trench (SPT) DRAM cell described by Lu et al. U.S. Pat. No. 4,688,063 as modified by Bronner et al. in U.S. Pat. No. 5,250,829. The cell includes a substrate 10 of P.sup.+ type semiconductor. A P well 12 is formed above an N isolation well 30. At the upper surface of the P well 12 a transfer device 14 is formed that includes a control gate 16 that is responsive to a word access line of the DRAM array support circuits, not shown. The transfer device 14 couples data between bit line diffused N.sup.+ region 18 and diffused N.sup.+ region 20 through the channel region formed in P well 12. A deep trench 22 is formed into the substrate 10, with deep trench 22 adjacent to N.sup.+ region 20. Inside deep trench 22 is formed the capacitor storage node comprising N.sup.+ type polysilicon electrode 24 isolated from substrate 10 by a thin dielectric layer. N.sup.+ region 20 and the polysilicon storage node 24 are connected by a conductive strap 11. At the top of the storage trench 22 is a thick isolating collar 28 which serves to prevent vertical leakage. These features are further refined in U.S. Pat. No. 5,264,716 "Double Well Substrate Plate Trench DRAM Cell Array" and U.S. Pat. No. 5,362,663 "Method of Forming Double Well Substrate Plate Trench DRAM Cell Array," (each issued to Bronner et al. and assigned to International Business Machines Corp.).
In these prior art designs, substrate 10 serves as a common plate counter electrode for all the integrated capacitors on this device. The prior art has consistently taught that the substrate 10 should comprise highly doped material. This was to minimize a number of problems associated with the trench capacitor. For example, as feature size shrinks, one of the major problems is capacitance loss due to depletion effects at the electrodes. Most capacitor designs try to achieve the highest possible doping of both the node and/or the plate to minimize depletion effects at the electrodes. In particular, prior art approaches have used heavily P.sub.+ substrates to minimize depletion effects with an P epitaxial layer on its top surface. The prior art thus taught that the doping of substrate 10 should generally be the maximum concentration of P dopants attainable by the wafer production process. This approach is successful at minimizing depletion effects but unfortunately leads to a less than favorable tradeoff between stored charge in the capacitor and the strength of the electric field in the dielectric.
Another prior art approach has been the use of a diffused region surrounding the deep trench as the capacitor counter electrode. These capacitors, commonly referred to as diffused plate capacitors, typically are able to achieve a relatively high capacitance with good reliability. Unfortunately, they require additional process steps to implement the diffused plate counter electrode.
Thus, the prior art suffers from the tradeoff between capacitance and reliability or requires excessive process complexity which creates a need for an improved capacitor design.